173 search results - page 12 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ISLPED
1995
ACM
15 years 1 months ago
1995
ACM
A dual-rail CMOS adiabatic switching circuit approach is described which follows the electroid model of Hall. These circuits can operate in either the retractile cascade or the re...
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
— This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, th...
PATMOS
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. Based on a previously reported request driven technique for Globally-Asynchronous Locally-Synchronous (GALS) circuits this paper presents two significant enhancements. Fi...
CDES
2006
14 years 11 months ago
2006
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
ICCD
2007
IEEE
15 years 1 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...