173 search results - page 15 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
89
Voted
DSD
2004
IEEE
15 years 1 months ago
2004
IEEE
Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power in a CMOS circuit is to reduce the number of transit...
GLVLSI
2002
IEEE
15 years 2 months ago
2002
IEEE
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
60
Voted
ASPDAC
2010
ACM
2010
ACM
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits
14 years 7 months ago
Abstract-- This paper presents an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using "canary flip-flop" that c...
75
Voted
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
ISLPED
2007
ACM
14 years 11 months ago
2007
ACM
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...