173 search results - page 17 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
63
Voted
ACSD
2010
IEEE
14 years 7 months ago
2010
IEEE
Abstract--Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step pr...
92
Voted
SBCCI
2009
ACM
15 years 4 months ago
2009
ACM
The purpose of this work is the proposal of a 10-Bit / 1 MSPS Analog to Digital Converter (ADC) with error correction to match the requirements of a CMOS wavefront sensor for opht...
122
click to vote
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
66
Voted
ISLPED
1996
ACM
15 years 1 months ago
1996
ACM
Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In thisp...