173 search results - page 19 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
ISLPED
2004
ACM
15 years 3 months ago
2004
ACM
The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniqu...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
IEEEPACT
2006
IEEE
15 years 3 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...