173 search results - page 20 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
76
Voted
DAC
2005
ACM
14 years 11 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
72
Voted
ICCD
2003
IEEE
15 years 6 months ago
2003
IEEE
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
VTS
2005
IEEE
15 years 3 months ago
2005
IEEE
: This project involves the design of a CMOS RF RMS Detector that converts the RMS voltage amplitude of an RF signal to a DC voltage. Its high input impedance and small area make i...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage ...
SIPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract— This paper is interested in applying voltage overscaling (VOS) to reduce trellis decoder energy consumption, where the key issue is how to minimize the decoding perform...