173 search results - page 22 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
106
Voted
EUC
2004
Springer
15 years 7 months ago
2004
Springer
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...
131
click to vote
DAC
2004
ACM
16 years 2 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
PATMOS
2004
Springer
15 years 7 months ago
2004
Springer
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
120
click to vote
DAC
2006
ACM
16 years 2 months ago
2006
ACM
Designing an energy efficient power gating structure is an important and challenging task in Multi-Threshold CMOS (MTCMOS) circuit design. In order to achieve a very low power des...
141
click to vote
ICCAD
2003
IEEE
15 years 10 months ago
2003
IEEE
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...