173 search results - page 23 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
HPCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
84
Voted
ICCAD
2010
IEEE
14 years 7 months ago
2010
IEEE
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switc...
74
Voted
FPGA
2004
ACM
15 years 3 months ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...