173 search results - page 24 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
ISCAS
2002
IEEE
15 years 2 months ago
2002
IEEE
The main result of this paper is the development of a low depth carry lookahead addition technique based on threshold logic. Two such adders are designed using the recently propos...
TVLSI
2002
14 years 9 months ago
2002
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
ISCA
2009
IEEE
15 years 4 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...