173 search results - page 27 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
105
click to vote
PATMOS
2007
Springer
15 years 3 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
TCAD
2008
14 years 9 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
This paper addresses the problem of low-power fanout optimization with multiple threshold voltage inverters. Introducing splitting and merging conversions that preserve delay, pow...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
Multi-threshold CMOS (MTCMOS) is an effective powergating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS switches. However, few ex...
69
Voted
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...