173 search results - page 28 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
NOCS
2009
IEEE
15 years 4 months ago
2009
IEEE
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
101
click to vote
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
- Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines...
71
Voted
DAC
2004
ACM
15 years 10 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...