173 search results - page 29 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
84
Voted
DAC
2004
ACM
15 years 1 months ago
2004
ACM
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
77
Voted
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
—Linear amplification with nonlinear components (LINC) technique is a linearization technique for power amplifier designs. By using LINC, the nonlinear power amplifier with high ...
VLSISP
2010
14 years 8 months ago
2010
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...