173 search results - page 30 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
The ability to do fine grain power management via local voltage selection has shown much promise via the use of Voltage/ Frequency Islands (VFIs). VFI-based designs combine the a...
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
65
Voted
CGO
2005
IEEE
15 years 3 months ago
2005
IEEE
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
70
Voted
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...
72
Voted
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...