173 search results - page 31 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
62
Voted
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
With the continued scaling of CMOS technologies and reduced design margins, the reliability concerns induced by transient faults have become prominent. Moreover, the popular energ...
86
Voted
ISCAS
2008
IEEE
15 years 4 months ago
2008
IEEE
— Long distance, low data-rate UWB communication for sensor network applications requires a highly energy efficient transceiver combined with circuit and system-level optimizati...
70
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
The Software-Defined Radio (SDR) concept aims to enabling costeffective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication ...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...