173 search results - page 33 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
SIPS
2008
IEEE
15 years 4 months ago
2008
IEEE
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
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Voted
EMSOFT
2007
Springer
15 years 3 months ago
2007
Springer
With multicore architectures being introduced to the market, the research community is revisiting problems to evaluate them under the new preconditions set by those new systems. A...
DFT
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...