173 search results - page 34 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
TDSC
2010
14 years 8 months ago
2010
—Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft ...
ICS
2005
Tsinghua U.
15 years 3 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
89
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ISLPED
2004
ACM
15 years 3 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
GLVLSI
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents a hybrid adiabatic content addressable memory (CAM). The CAM uses an adiabatic switching technique to reduce the energy consumption in the match line while kee...
172
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VLDB
2007
ACM
15 years 10 months ago
2007
ACM
Similarity-based search over time-series databases has been a hot research topic for a long history, which is widely used in many applications, including multimedia retrieval, dat...