173 search results - page 4 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ICCAD
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
RTAS
2000
IEEE
15 years 2 months ago
2000
IEEE
—Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fa...
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
ISLPED
2004
ACM
15 years 3 months ago
2004
ACM
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a ...
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ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...