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    » Power Reducing Techniques for Clocked CMOS PLAs
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    ASPDAC
    2007
    ACM
    107views Hardware» more  ASPDAC 2007»
    A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
    15 years 1 months ago
    A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
    Download  www.cecs.uci.edu
    Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
    Seongmoon Wang, Wenlong Wei
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    DATE
    2006
    IEEE
    176views Hardware» more  DATE 2006»
    Low power synthesis of dynamic logic circuits using fine-grained clock gating
    15 years 3 months ago
    Low power synthesis of dynamic logic circuits using fine-grained clock gating
    Download  online.sfsu.edu
    — Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
    Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...
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    ISCAS
    2006
    IEEE
    135views Hardware» more  ISCAS 2006»
    Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies
    15 years 3 months ago
    Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies
    Download  ihome.ust.hk
    A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
    Volkan Kursun, Zhiyu Liu
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    ISLPED
    1999
    ACM
    177views Hardware» more  ISLPED 1999»
    Low power synthesis of dual threshold voltage CMOS VLSI circuits
    15 years 2 months ago
    Low power synthesis of dual threshold voltage CMOS VLSI circuits
    Download  www.cecs.uci.edu
    The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
    Vijay Sundararajan, Keshab K. Parhi
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    ISLPED
    2000
    ACM
    92views Hardware» more  ISLPED 2000»
    Low power sequential circuit design by using priority encoding and clock gating
    15 years 1 months ago
    Low power sequential circuit design by using priority encoding and clock gating
    Download  atrak.usc.edu
    This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
    Xunwei Wu, Massoud Pedram
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