173 search results - page 7 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
Extensive research has proposed the use of multiple on-die power supplies (VDD) for reducing power consumption in CMOS circuits. We present a detailed study and design techniques ...
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CORR
2010
Springer
14 years 9 months ago
2010
Springer
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
ISLPED
2000
ACM
15 years 2 months ago
2000
ACM
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...
ICCD
2008
IEEE
15 years 4 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
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ASPDAC
1995
ACM
15 years 1 months ago
1995
ACM
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...