173 search results - page 8 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
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RTSS
1998
IEEE
15 years 1 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
ISLPED
1999
ACM
15 years 2 months ago
1999
ACM
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
ICCAD
1996
IEEE
15 years 1 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
MJ
2007
14 years 9 months ago
2007
Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the successful deployment of SAT technology in a wi...
EH
2002
IEEE
15 years 2 months ago
2002
IEEE
The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5GHz have been reported. However, to make the idea practical, serious power management an...