173 search results - page 9 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
62
Voted
ISLPED
2007
ACM
14 years 11 months ago
2007
ACM
Throughput servers using simultaneous multithreaded (SMT) processors are becoming an important paradigm with products such as Sun's Niagara and IBM Power5. Unfortunately, thr...
PACS
2000
Springer
15 years 1 months ago
2000
Springer
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
TVLSI
1998
14 years 9 months ago
1998
— Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efï...
ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
96
Voted
GLVLSI
1998
IEEE
15 years 1 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...