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» Power analysis of embedded operating systems
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ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
15 years 2 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
DAC
2008
ACM
15 years 10 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
MAM
2002
110views more  MAM 2002»
14 years 9 months ago
Architecture of a fieldbus message scheduler coprocessor based on the planning paradigm
The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeline...
Ernesto Martins, Paulo A. C. S. Neves, José...
ICDE
2010
IEEE
198views Database» more  ICDE 2010»
15 years 3 months ago
Power-aware data analysis in sensor networks
Abstract— Sensor networks have evolved to a powerful infrastructure component for event monitoring in many application scenarios. In addition to simple filter and aggregation op...
Daniel Klan, Katja Hose, Marcel Karnstedt, Kai-Uwe...
EH
2003
IEEE
117views Hardware» more  EH 2003»
15 years 3 months ago
The Evolutionary Design and Synthesis of Non-Linear Digital VLSI Systems
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
Robert Thomson, Tughrul Arslan