115 search results - page 11 / 23 » Power analysis of system-level on-chip communication archite... |
86
Voted
DAC
2007
ACM
16 years 20 days ago
2007
ACM
Packet-switched networks on chip (NoC) have been advocated as a natural communication mechanism among the processing cores in future chip multiprocessors (CMP). However, electroni...
100
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VTC
2006
IEEE
15 years 5 months ago
2006
IEEE
— In this paper we present extremely flexible and low power digital binary ASK, PSK, and FSK demodulator architectures for short-range applications that uses limiter amplifier (i...
116
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ICEIS
2000
IEEE
15 years 4 months ago
2000
IEEE
We understand distributed systems as a collection of distributed computation resources that work together as one harmonious system. It is the great achievement of computer network...
DAC
2003
ACM
15 years 5 months ago
2003
ACM
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
89
Voted
GLVLSI
2010
IEEE
15 years 4 months ago
2010
IEEE
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...