115 search results - page 6 / 23 » Power analysis of system-level on-chip communication archite... |
EUROMICRO
2000
IEEE
15 years 4 months ago
2000
IEEE
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
105
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DAC
1997
ACM
15 years 3 months ago
1997
ACM
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
133
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VLSID
2001
IEEE
16 years 16 hour ago
2001
IEEE
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
MEMOCODE
2003
IEEE
15 years 4 months ago
2003
IEEE
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
117
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CODES
2003
IEEE
15 years 5 months ago
2003
IEEE
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...