115 search results - page 9 / 23 » Power analysis of system-level on-chip communication archite... |
ICPP
2009
IEEE
15 years 6 months ago
2009
IEEE
Abstract—This paper analyzes energy characteristics of parallel algorithms executed on scalable multicore processors. Specifically, we provide a methodology for evaluating energ...
105
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CODES
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
99
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DFT
2005
IEEE
15 years 5 months ago
2005
IEEE
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
114
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VTC
2010
IEEE
14 years 10 months ago
2010
IEEE
—In this paper we present an architectural analysis of a smart DMA (sDMA) controller for protocol stack acceleration in mobile devices supporting 3GPP’s Long Term Evolution (LT...
ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...