997 search results - page 155 / 200 » Power and Area Optimization for Multiple Restricted Multipli... |
107
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IWOMP
2007
Springer
15 years 3 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
VTC
2007
IEEE
15 years 4 months ago
2007
IEEE
—The exploitation of multiuser diversity and the application of multiple antennas at transmitter and receiver are considered to be key technologies for future highly bandwidtheff...
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
117
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TVLSI
2010
14 years 4 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
VSTTE
2005
Springer
15 years 3 months ago
2005
Springer
The validation of modern software systems on mobile devices needs to incorporate both functional and non-functional requirements. While some progress has been made in validating pe...