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» Power and cost aware distributed load management
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CASES
2006
ACM
15 years 3 months ago
FlashCache: a NAND flash memory file cache for low power web servers
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
Taeho Kgil, Trevor N. Mudge
DATE
2007
IEEE
148views Hardware» more  DATE 2007»
15 years 3 months ago
Temperature aware task scheduling in MPSoCs
In deep submicron circuits, elevation in temperatures has brought new challenges in reliability, timing, performance, cooling costs and leakage power. Conventional thermal managem...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith...
ISCA
2003
IEEE
168views Hardware» more  ISCA 2003»
15 years 2 months ago
Temperature-Aware Microarchitecture
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakuma...
SC
2005
ACM
15 years 3 months ago
Performance-constrained Distributed DVS Scheduling for Scientific Applications on Power-aware Clusters
Left unchecked, the fundamental drive to increase peak performance using tens of thousands of power hungry components will lead to intolerable operating costs and failure rates. H...
Rong Ge, Xizhou Feng, Kirk W. Cameron
IEEEPACT
2008
IEEE
15 years 3 months ago
Multi-optimization power management for chip multiprocessors
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
Ke Meng, Russ Joseph, Robert P. Dick, Li Shang