1850 search results - page 103 / 370 » Power and performance optimization at the system level |
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
TWC
2008
14 years 9 months ago
2008
In modern wireless communication systems, power control plays a fundamental role for efficient resource utilization, in particular in the systems where the users share the same ban...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
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CC
2012
Springer
13 years 5 months ago
2012
Springer
Abstract. Data-parallel languages like OpenCL and CUDA are an important means to exploit the computational power of today’s computing devices. In this paper, we deal with two asp...