1850 search results - page 104 / 370 » Power and performance optimization at the system level |
VLSID
2006
IEEE
15 years 3 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
CASES
2006
ACM
15 years 3 months ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
CASES
2001
ACM
15 years 1 months ago
2001
ACM
The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent ...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...