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» Power and performance optimization at the system level
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MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
14 years 7 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
ICCD
2007
IEEE
157views Hardware» more  ICCD 2007»
15 years 6 months ago
Limits on voltage scaling for caches utilizing fault tolerant techniques
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M...
TWC
2008
120views more  TWC 2008»
14 years 9 months ago
Binary Power Control for Sum Rate Maximization over Multiple Interfering Links
We consider allocating the transmit powers for a wireless multi-link (N-link) system, in order to maximize the total system throughput under interference and noise impairments, and...
Anders Gjendemsjø, David Gesbert, Geir E. &...
IJCNN
2007
IEEE
15 years 4 months ago
Symmetric Kernel Detector for Multiple-Antenna Aided Beamforming Systems
— We propose a powerful symmetric kernel classifier for nonlinear detection in challenging rank-deficient multipleantenna aided communication systems. By exploiting the inheren...
Sheng Chen, Andreas Wolfgang, Chris J. Harris, Laj...

Publication
1169views
16 years 3 months ago
Image Enhancement for Backlight-Scaled TFT-LCD Displays
One common way to extend the battery life of a portable device is to reduce the LCD backlight intensity. In contrast to previous approaches that minimize the power consumption by a...
Pei-Shan Tsai, Chia-Kai Liang, Tai-Hsiang Huang, a...