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» Power and performance optimization at the system level
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GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
FPL
2001
Springer
102views Hardware» more  FPL 2001»
15 years 2 months ago
Technology Trends and Adaptive Computing
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...
Michael J. Flynn, Albert A. Liddicoat
TWC
2008
188views more  TWC 2008»
14 years 9 months ago
Joint power control and beamforming for cognitive radio networks
We consider a secondary usage of spectrum scenario where a secondary network coexists and/or shares the radio spectrum with a primary network to which the spectrum is licensed. The...
Habibul Islam, Ying-Chang Liang, Anh Tuan Hoang
ICS
2007
Tsinghua U.
15 years 4 months ago
Optimization and bottleneck analysis of network block I/O in commodity storage systems
Building commodity networked storage systems is an important architectural trend; Commodity servers hosting a moderate number of consumer-grade disks and interconnected with a hig...
Manolis Marazakis, Vassilis Papaefstathiou, Angelo...
DOCENG
2003
ACM
15 years 3 months ago
Improving formatting documents by coupling formatting systems
In this paper, we present a framework for coupling an existing formatting system such as SMIL [7] and Madeus [13] with a formatting control system XEF [10]. This framework allows ...
Fateh Boulmaiz, Cécile Roisin, Fréd&...