Sciweavers

1850 search results - page 114 / 370
» Power and performance optimization at the system level
Sort
View
ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
15 years 6 months ago
Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm
In this work, we propose a dynamic power-aware issue queue in a general-purpose microprocessor for multimedia applications. Its resources can be adapted at runtime in accordance w...
Yu Bai, R. Iris Bahar
CONCURRENCY
2006
140views more  CONCURRENCY 2006»
14 years 10 months ago
An efficient memory operations optimization technique for vector loops on Itanium 2 processors
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
ISSS
1999
IEEE
109views Hardware» more  ISSS 1999»
15 years 2 months ago
Loop Alignment for Memory Accesses Optimization
Portable or embedded systems allow more and more complex applications like multimedia today. These applications and submicronic technologies have made the power consumption criter...
Antoine Fraboulet, Guillaume Huard, Anne Mignotte
USENIX
2008
15 years 7 days ago
FlexVol: Flexible, Efficient File Volume Virtualization in WAFL
zation is a well-known method of abstracting physical resources and of separating the manipulation and use of logical resources from their underlying implementation. We have used ...
John K. Edwards, Daniel Ellard, Craig Everhart, Ro...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
15 years 10 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...