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» Power and performance optimization at the system level
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ISPASS
2010
IEEE
15 years 4 months ago
Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor
After many years of prefetching research, most commercially available systems support only two types of prefetching: software-directed prefetching and hardware-based prefetchers u...
Harold W. Cain, Priya Nagpurkar
ECBS
2007
IEEE
107views Hardware» more  ECBS 2007»
15 years 4 months ago
Motion Planning System for Minimally Invasive Surgery
Minimally invasive procedures are highly effective when performed by well trained surgeons. However, with the subjective nature of surgical training and performance assessment, it...
Hanees Haniffa, Jerzy W. Rozenblit, Jianfeng Peng,...
DAC
2002
ACM
15 years 11 months ago
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
Patrick Schaumont, Henry Kuo, Ingrid Verbauwhede
GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
15 years 4 months ago
A simulation methodology for reliability analysis in multi-core SoCs
Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to high...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf...
IWCMC
2006
ACM
15 years 3 months ago
Budgeting power: packet duplication and bit error rate reduction in wireless ad-hoc networks
In this paper we present and evaluate a new technique to lower packet-level error rates of application layer connections in wireless ad-hoc networks. In our scheme, data packets s...
Ghassen Ben Brahim, Bilal Khan