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» Power and performance optimization at the system level
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IPPS
1998
IEEE
15 years 2 months ago
Compiler-Optimization of Implicit Reductions for Distributed Memory Multiprocessors
This paper presents reduction recognition and parallel code generationstrategies for distributed-memorymultiprocessors. We describe techniques to recognize a broad range of implic...
Bo Lu, John M. Mellor-Crummey
DATE
2005
IEEE
111views Hardware» more  DATE 2005»
14 years 12 months ago
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
WOSP
2010
ACM
15 years 4 months ago
SLA-driven planning and optimization of enterprise applications
We propose a model-based methodology to size and plan enterprise applications under Service Level Agreements (SLAs). Our approach is illustrated using a real-world Enterprise Reso...
Hui Li, Giuliano Casale, Tariq N. Ellahi
GLOBECOM
2007
IEEE
14 years 11 months ago
The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation
: The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turne...
Min Li, Bruno Bougard, Eduardo Lopez-Estraviz, And...
ICCD
2008
IEEE
175views Hardware» more  ICCD 2008»
15 years 6 months ago
On-chip high performance signaling using passive compensation
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lin...
Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori ...