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» Power and performance optimization at the system level
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ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 3 months ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
PVLDB
2010
204views more  PVLDB 2010»
14 years 8 months ago
Cheetah: A High Performance, Custom Data Warehouse on Top of MapReduce
Large-scale data analysis has become increasingly important for many enterprises. Recently, a new distributed computing paradigm, called MapReduce, and its open source implementat...
Songting Chen
CODES
1999
IEEE
15 years 2 months ago
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages
raction levels of communication models to allow designers to trade off between performance and accuracy. Contrary to [2][3], we present an optimization method which preserves the a...
Sungjoo Yoo, Kiyoung Choi
MICRO
2002
IEEE
171views Hardware» more  MICRO 2002»
15 years 2 months ago
Orion: a power-performance simulator for interconnection networks
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad...
ACSD
2006
IEEE
102views Hardware» more  ACSD 2006»
14 years 12 months ago
Models of Computation for Networks on Chip
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
Axel Jantsch