1850 search results - page 14 / 370 » Power and performance optimization at the system level |
95
Voted
ICUMT
2009
14 years 7 months ago
2009
Uplink users in cellular networks, such as UMTS/ HSPA, located at the edge of the cell generally suffer from poor channel conditions. Deploying intermediate relay nodes is seen as ...
CODES
2008
IEEE
14 years 9 months ago
2008
IEEE
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
ISSS
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
HOTOS
1999
IEEE
15 years 1 months ago
1999
IEEE
Reducing the energy consumed in the use of computing devices is becoming a major design challenge. While the problem obviously must be addressed with improved low-level technology...