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» Power and performance optimization at the system level
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SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
15 years 4 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
ICC
2007
IEEE
15 years 4 months ago
Space-Time Coded Systems with Joint Transmit and Receive Antenna Selection
— This paper studies performance of space-time coded (STC) systems with joint transmit and receive antenna selection over multiple input multiple output (MIMO) flat and frequenc...
Tansal Gucluoglu, Tolga M. Duman
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
15 years 4 months ago
System-level scheduling on instruction cell based reconfigurable systems
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawa...
RTSS
2006
IEEE
15 years 4 months ago
Delay Analysis in Temperature-Constrained Hard Real-Time Systems with General Task Arrivals
In this paper, we study temperature-constrained hard realtime systems, where real-time guarantees must be met without exceeding safe temperature levels within the processor. Dynam...
Shengquan Wang, Riccardo Bettati
CC
1999
Springer
107views System Software» more  CC 1999»
15 years 2 months ago
Link-Time Improvement of Scheme Programs
Abstract. Optimizing compilers typically limit the scope of their analyses and optimizations to individual modules. This has two drawbacks: rst, library code cannot be optimized to...
Saumya K. Debray, Robert Muth, Scott A. Watterson