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» Power and performance optimization at the system level
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ISCA
2007
IEEE
113views Hardware» more  ISCA 2007»
15 years 4 months ago
Thermal modeling and management of DRAM memory systems
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard Da...
JCP
2008
216views more  JCP 2008»
14 years 10 months ago
Design Overview Of Processor Based Implantable Pacemaker
Implantable pacemaker is a battery operated real time embedded system, which includes software/hardware codesign strategy. As it is placed within the heart by surgery, battery life...
Santosh D. Chede, Kishore D. Kulat
DCC
2010
IEEE
15 years 5 months ago
Optimized Analog Mappings for Distributed Source-Channel Coding
This paper focuses on optimal analog mappings for zero-delay, distributed source-channel coding. The objective is to obtain the optimal vector transformations that map between m-d...
Emrah Akyol, Kenneth Rose, Tor A. Ramstad
PPSN
1998
Springer
15 years 2 months ago
A Decoder-Based Evolutionary Algorithm for Constrained Parameter Optimization Problems
Several methods have been proposed for handling nonlinear constraints by evolutionary algorithms for numerical optimization problems; a survey paper [7] provides an overview of var...
Slawomir Koziel, Zbigniew Michalewicz
JSA
2008
91views more  JSA 2008»
14 years 10 months ago
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...
Ehsan Atoofian, Amirali Baniasadi