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» Power and performance optimization at the system level
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ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
16 years 18 days ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
COMGEO
1999
ACM
15 years 5 months ago
Visualizing geometric algorithms over the Web
The visual nature of geometry applications makes them a natural area where visualization can be an effective tool for demonstrating algorithms. In this paper we propose a new mode...
James E. Baker, Isabel F. Cruz, Giuseppe Liotta, R...
ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
15 years 9 months ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...
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ARITH
2005
IEEE
15 years 11 months ago
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
Silvia M. Müller, Christian Jacobi 0002, Hwa-...
PIMRC
2008
IEEE
16 years 14 days ago
Combining MIMO and relaying gains for highly efficient wireless backhaul
— In this paper, the design of a highly efficient and flexibly deployable wireless backhaul is addressed as a promising alternative to the typical wired solutions. To this end, a...
Angeliki Alexiou, Kai Yu, Federico Boccardi