1850 search results - page 211 / 370 » Power and performance optimization at the system level |
157
click to vote
PIMRC
2008
IEEE
16 years 16 days ago
2008
IEEE
—Suboptimal detection schemes, such as list MIMO detection, often face the challenge of having to “guess” at the decision reliability for some of the detected bits. A simple ...
149
click to vote
TIFS
2008
15 years 6 months ago
2008
A framework is proposed for synchronization in feature-based data embedding systems that is tolerant of errors in estimated features. The method combines feature-based embedding wi...
162
click to vote
DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
178
click to vote
ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
158
click to vote
CLUSTER
2004
IEEE
15 years 10 months ago
2004
IEEE
Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop un...