Sciweavers

1850 search results - page 218 / 370
» Power and performance optimization at the system level
Sort
View
ISCA
2010
IEEE
163views Hardware» more  ISCA 2010»
15 years 11 months ago
WiDGET: Wisconsin decoupled grid execution tiles
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
Yasuko Watanabe, John D. Davis, David A. Wood
ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
15 years 10 months ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf
167
Voted
DAC
2002
ACM
16 years 7 months ago
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer
201
Voted
SASP
2008
IEEE
183views Hardware» more  SASP 2008»
16 years 19 days ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
CIVR
2008
Springer
245views Image Analysis» more  CIVR 2008»
15 years 8 months ago
Probabilistic optimized ranking for multimedia semantic concept detection via RVM
We present a probabilistic ranking-driven classifier for the detection of video semantic concept, such as airplane, building, etc. Most existing concept detection systems utilize ...
Yantao Zheng, Shi-Yong Neo, Tat-Seng Chua, Qi Tian