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» Power and performance optimization at the system level
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ERSA
2008
185views Hardware» more  ERSA 2008»
15 years 7 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George
137
Voted
ICC
2007
IEEE
16 years 14 days ago
A New MIMO Beamforming Technique Based on Rotation Transformations
Abstract— In this paper, we propose a new transmit beamforming technique for multiple-input-multiple-output (MIMO) systems to improve the link level performance. We present a met...
Heunchul Lee, Seokhwan Park, Inkyu Lee
142
Voted
DATE
2010
IEEE
192views Hardware» more  DATE 2010»
15 years 11 months ago
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, ...
ICML
1995
IEEE
16 years 7 months ago
Learning to Make Rent-to-Buy Decisions with Systems Applications
In the single rent-to-buy decision problem, without a priori knowledge of the amount of time a resource will be used we need to decide when to buy the resource, given that we can ...
P. Krishnan, Philip M. Long, Jeffrey Scott Vitter
ICEC
1994
82views more  ICEC 1994»
15 years 7 months ago
Improving Search by Incorporating Evolution Principles in Parallel Tabu Search
Combinatorial optimization problems require computing efforts which grow at least exponentially with the problem dimension. Therefore, the use of the remarkable power of massively...
Ivan De Falco, Renato Del Balio, Ernesto Tarantino...