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» Power and performance optimization at the system level
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CGO
2005
IEEE
15 years 11 months ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
ICCD
2006
IEEE
171views Hardware» more  ICCD 2006»
16 years 3 months ago
Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach
This paper proposes a stochastic dynamic thermal management (DTM) technique in high-performance VLSI system with especial attention to the uncertainty in temperature observation. ...
Hwisung Jung, Massoud Pedram
HPDC
2002
IEEE
15 years 11 months ago
Evaluating Web Services Based Implementations of GridRPC
GridRPC is a class of Grid middleware for scientific computing. Interoperability has been an important issue, because current GridRPC systems each employ its own protocol. Web se...
Satoshi Shirasuna, Hidemoto Nakada, Satoshi Matsuo...
192
Voted
CASES
2005
ACM
15 years 8 months ago
Segment protection for embedded systems using run-time checks
The lack of virtual memory protection is a serious source of unreliability in many embedded systems. Without the segment-level protection it provides, these systems are subject to...
Matthew Simpson, Bhuvan Middha, Rajeev Barua
298
Voted
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
15 years 11 months ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun