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» Power and performance optimization at the system level
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VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
15 years 10 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
DAC
2007
ACM
15 years 10 months ago
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
Behnam Amelifard, Massoud Pedram
PPOPP
2005
ACM
15 years 3 months ago
Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, A...
EH
2004
IEEE
117views Hardware» more  EH 2004»
15 years 1 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
66
Voted
DSD
2004
IEEE
104views Hardware» more  DSD 2004»
15 years 1 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...