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» Power and performance optimization at the system level
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VLSISP
2008
104views more  VLSISP 2008»
14 years 11 months ago
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Data dominated signal processing applications are typically described using large and multi-dimensional arrays and loop nests. The order of production and consumption of array ele...
Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verd...
IEEEPACT
2005
IEEE
15 years 5 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove
CASES
2004
ACM
15 years 5 months ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder
SIGMOD
2009
ACM
202views Database» more  SIGMOD 2009»
16 years 3 days ago
ZStream: a cost-based query processor for adaptively detecting composite events
Composite (or Complex) event processing (CEP) systems search sequences of incoming events for occurrences of userspecified event patterns. Recently, they have gained more attentio...
Yuan Mei, Samuel Madden
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
15 years 3 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri