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» Power and performance optimization at the system level
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ICEIS
2000
IEEE
15 years 4 months ago
Architectural Considerations with Distributed Computing
We understand distributed systems as a collection of distributed computation resources that work together as one harmonious system. It is the great achievement of computer network...
Yibing Wang, Robert M. Hyatt, Barrett R. Bryant
JUCS
2006
112views more  JUCS 2006»
14 years 12 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
VIS
2004
IEEE
135views Visualization» more  VIS 2004»
16 years 1 months ago
Adaptive 4-8 Texture Hierarchies
We address the texture level-of-detail problem for extremely large surfaces such as terrain during realtime, view-dependent rendering. A novel texture hierarchy is introduced base...
Kenneth I. Joy, Lok M. Hwa, Mark A. Duchaineau
VTC
2008
IEEE
117views Communications» more  VTC 2008»
15 years 6 months ago
Design of Rate Constrained Multi-User Receivers for Satellite Communications
—In the realm of satellite communications, one of the great impairments to increase the spectral efficiency is multi-user interference in the reverse link (mobile to satellite). ...
Sami Mekki, Mérouane Debbah
HPCA
2003
IEEE
16 years 8 days ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston