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» Power and performance optimization at the system level
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CODES
2006
IEEE
15 years 6 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
ICIP
2001
IEEE
16 years 1 months ago
Non-sequential video structuring based on video object linking: an efficient tool for video browsing and indexing
An efficient system for unsupervised structuring of stereoscopic sequences is presented in this paper, which generates links between similar VOPs of different shots. Particularly ...
Klimis S. Ntalianis, Nikolaos D. Doulamis, Anastas...
LCTRTS
2007
Springer
15 years 6 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
DAWAK
2006
Springer
15 years 3 months ago
Extending Visual OLAP for Handling Irregular Dimensional Hierarchies
Comprehensive data analysis has become indispensable in a variety of environments. Standard OLAP (On-Line Analytical Processing) systems, designed for satisfying the reporting need...
Svetlana Mansmann, Marc H. Scholl
PADS
2003
ACM
15 years 5 months ago
Scalable RTI-Based Parallel Simulation of Networks
Federated simulation interfaces such as the High Level Architecture (HLA) were designed for interoperability, and as such are not traditionally associated with highperformance com...
Kalyan S. Perumalla, Alfred Park, Richard M. Fujim...