1850 search results - page 321 / 370 » Power and performance optimization at the system level |
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, we present a methodology for profiling parallel applications executing on the IBM PowerXCell 8i (commonly referred to as the “Cell” processor). Specifically, we...
IROS
2007
IEEE
15 years 4 months ago
2007
IEEE
— We present a refined, second-generation design, construction and integration, of a compact hyper-redundant snakelike robot, called “Woodstock.” This robot has substantial a...
IWANN
1995
Springer
15 years 1 months ago
1995
Springer
1 This paper presents a new technique for the design of real-time controllers based on a hybrid approach which integrates several control strategies, such as intelligent controlle...
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FPGA
2007
ACM
15 years 3 months ago
2007
ACM
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...