Sciweavers

1850 search results - page 39 / 370
» Power and performance optimization at the system level
Sort
View
73
Voted
IPPS
2002
IEEE
15 years 2 months ago
A Parallel Two-Level Hybrid Method for Diagonal Dominant Tridiagonal Systems
A new method, namely the Parallel Two-Level Hybrid (PTH) method, is developed to solve tridiagonal systems on parallel computers. PTH is designed based on Parallel Diagonal Domina...
Xian-He Sun, Wu Zhang
AHS
2007
IEEE
251views Hardware» more  AHS 2007»
15 years 1 months ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
85
Voted
VTC
2007
IEEE
146views Communications» more  VTC 2007»
15 years 3 months ago
Orthogonal STBC in General Nakagami-m Fading Channels: BER Analysis and Optimal Power Allocation
Abstract— We analyze the performance of multiple-input multiple-output (MIMO) systems employing orthogonal space-time block codes (STBC) in general Nakagami-m fading channels wit...
Andreas Müller, Joachim Speidel
93
Voted
ENTCS
2008
131views more  ENTCS 2008»
14 years 9 months ago
Connector Rewriting with High-Level Replacement Systems
Reo is a language for coordinating autonomous components in distributed environments. Coordination in Reo is performed by circuit-like connectors, which are constructed from primi...
Christian Koehler, Alexander Lazovik, Farhad Arbab
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 3 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...