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» Power and performance optimization at the system level
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GLOBECOM
2009
IEEE
15 years 4 months ago
Joint Power Control and Beamforming Codebook Design for MISO Channels with Limited Feedback
Abstract— This paper investigates the joint design and optimization of the power control and beamforming codebooks for the single-user multiple-input single-output (MISO) wireles...
Behrouz Khoshnevis, Wei Yu
SIGMETRICS
2010
ACM
187views Hardware» more  SIGMETRICS 2010»
15 years 2 months ago
Can multipath mitigate power law delays?: effects of parallelism on tail performance
—Parallelism has often been used to improve the reliability and efficiency of a variety of different engineering systems. In this paper, we quantify the efficiency of paralleli...
Jian Tan, Wei Wei, Bo Jiang, Ness Shroff, Donald F...
ICCAD
2001
IEEE
256views Hardware» more  ICCAD 2001»
15 years 6 months ago
An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems
Once the battery becomes fully discharged, a battery-powered portable electronic system goes off-line. Therefore, it is important to take the battery behavior into account. A syst...
Daler N. Rakhmatov, Sarma B. K. Vrudhula
SAMOS
2004
Springer
15 years 3 months ago
High-Level Energy Estimation for ARM-Based SOCs
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
73
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VLSID
2000
IEEE
79views VLSI» more  VLSID 2000»
15 years 2 months ago
Inductive Noise Reduction at the Architectural Level
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...