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» Power and performance optimization at the system level
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VLSID
2002
IEEE
105views VLSI» more  VLSID 2002»
15 years 10 months ago
A Heuristic for Clock Selection in High-Level Synthesis
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
KESAMSTA
2007
Springer
15 years 3 months ago
Quantitative Analysis of Single-Level Single-Mediator Multi-agent Systems
Queueing Theory deals with problems where some restricted resource should be shared between competitive flow of requests. In this paper we use Queueing Theory methods to perform a...
Moon Ho Lee, Aliaksandr Birukou, Alexander N. Dudi...
VTC
2010
IEEE
404views Communications» more  VTC 2010»
14 years 8 months ago
Power Efficient Dynamic Resource Scheduling Algorithms for LTE
: This paper presents a link level analysis of the rate and energy efficiency performance of the LTE downlink considering the unitary codebook based precoding scheme. In a multi-us...
Congzheng Han, Kian Chung Beh, Marios Nicolaou, Si...
LCTRTS
2001
Springer
15 years 2 months ago
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
Dong-In Kang, Stephen P. Crago, Jinwoo Suh
LCPC
2000
Springer
15 years 1 months ago
Optimizing the Use of High Performance Software Libraries
Abstract. This paper describes how the use of software libraries, which is prevalent in high performance computing, can benefit from compiler optimizations in much the same way tha...
Samuel Z. Guyer, Calvin Lin